The CANopenIA-M0 implements the CANopen protocol compliant to the CiA standards
- CiA301 version 4.2 (CANopen application layer and communication profile),
- CiA305 version 2.2.14 (Layer setting services and protocols) and
- CiA401 version 3.0 (Device profile for generic I/O modules).
CANopenIA-M0 is based on the NXP Cortex M0 32-bit micro controller. A derivative with integrated CAN transceiver is used to minimize the external components needed around the protocol chip. The Cortex architecture in conjunction with the optimized firmware design results in a very high performance. Time delays between in our outgoing CAN PDOs and hardware events are brought down to 15 micro seconds.
This high performant and ready to use CANopen solution is available as a chip or as a module. The module implements around the chip the clock generation, a serial EEPROM to store the configuration data and two LEDs to signal the CANopen state. To become familiar with COIA-M0 a starter kit and an evaluation kit are available.
Entries in the object dictionary, the I/O ports and the SDO and PDO behavior is configured with a straightforward setup utility or the CANopen Architect EDS editor..